1. Field
The application relate to a semiconductor integrated circuit having a differential amplifier which amplifies a voltage difference in a data line pair.
2. Description of the Related Art
In a semiconductor integrated circuit, for example a semiconductor memory such as DRAM, data read from a memory cell are transmitted to one of a bit line pair. At this time, the other of the bit line pair is precharged to the reference voltage. Then, data are read by amplifying the voltage difference in the bit line pair by a sense amplifier and taking out the amplified signal.
In Japanese Laid-open Patent Publication No. 2000-36194 and Japanese Laid-open Patent Publication No. S63-42095, there is disclosed a circuit which precharges a bit line on the reference side until just before the sense amplifier operates. Specifically, bit lines are coupled to a reference voltage line by switching transistors which operate independently from each other. Thus, when a read operation is performed, change of the voltage on the bit line on the reference side due to the coupling capacitance between the bit lines is prevented. That is, decrease of the voltage difference in the bit line pair is prevented.
In recent years, due to miniaturization of device structures, the areas of memory cells decrease, and the interval between bit lines tends to be narrow. Accordingly, the coupling capacitance between bit lines tends to increase. Further, when the interval between bit lines becomes narrow, it becomes difficult to increase the sizes of precharge transistors arranged in a memory cell array. It hinders increasing of driving power of the precharge transistors. Furthermore, between a transistor and bit lines/a reference voltage line, there exist a resistance component such as contact resistance and/or a capacitance component such as diffusion capacitance. Accordingly, due to the miniaturization, it is becoming more and more difficult to cancel the operation of the coupling capacitance when read data are transmitted to one bit line so as to match the other bit line with the precharge voltage.
In addition, for reducing the chip size, there is proposed a semiconductor memory in which memory cell arrays are arranged on both sides of a sense amplifier, and the sense amplifier is shared by the memory cell arrays. However, in this type of semiconductor memory, there is no technology proposed for reducing the influence of the coupling capacitance between bit lines.